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ltc4000-1 1 40001f solar panel input regulation, achieves max power point to greater than 98% typical a pplica t ion fea t ures descrip t ion high voltage high current controller for battery charging with maximum power point control the lt c ? 4000-1 is a high voltage, high performance controller that converts many externally compensated dc/dc power supplies into full-featured battery chargers with maximum power point control. in contrast to the ltc4000, the ltc4000-1 has an input voltage regulation loop instead of the input current regulation loop. features of the ltc4000-1s battery charger include: accurate (0.25%) programmable float voltage, select- able timer or current termination, temperature qualified charging using an ntc thermistor, automatic recharge, c/10 trickle charge for deeply discharged cells, bad battery detection and status indicator outputs. the battery charger also includes precision current sensing that allows lower sense voltages for high current applications. the ltc4000-1 supports intelligent powerpath control. an external pfet provides low loss reverse current protec- tion. another external pfet provides low loss charging or discharging of the battery. this second pfet also facilitates an instant-on feature that provides immediate downstream system power even when connected to a heavily discharged or shorted battery. the ltc4000-1 is available in a low profile 28- lead 4mm 5mm qfn and ssop packages. 10.8v at 10a charger for three lifepo 4 cells with a solar panel input a pplica t ions n maximum power control: solar panel input compatible n complete high performance battery charger when paired with a dc/dc converter n wide input and output voltage range: 3v to 60v n input ideal diode for low loss reverse blocking and load sharing n output ideal diode for low loss powerpath? and load sharing with the battery n programmable charge current: 1% accuracy n 0.25% accurate programmable float v oltage n programmable c/x or t imer based charge termination n ntc input for temperature qualified charging n 28-lead 4mm 5mm qfn or ssop packages n solar powered battery charger systems n battery charger with high impedance input source, e.g., fuel cell or wind t urbine n battery equipped industrial or portable military equipments l, lt , lt c , lt m , linear technology and the linear logo are registered trademarks and powerpath is a trademark of linear technology corporation. all other trademarks are the property of their respective owners. 1.13m 14.7k 127k 10k 10k 3-cell lifepo 4 battery pack v bat 10.8v float 10a max charge current 1.15m 47nf 5m v out 12v, 15a solar panel input <60v open circuit voltage 17.6v peak power voltage si7135dp 133k csn csp bgate igate bat ofb fbg bfb ntc cx ltc4000-1 ith cc iid 5m lt3845a 100f out v c in cln in ifb 22.1k tmr iimon gnd bias cl 24.9k 1f 3v 332k 20k 1f 10nf 40001 ta01a si7135dp 0.1f charger output current: i rcs (a) 1 10 input regulation voltage: v inreg (v) 12 16 14 18 20 5 6 7 8 9 40001 ta01b 10 2 3 4 t a = 25c 98% to 95% peak power 100% to 98% peak power
ltc4000-1 2 40001f a bsolu t e maxi m u m r a t ings in , cln , iid , csp , csn , bat ....................... C 0.3 v to 62 v in - cln , csp - csn ............................................ C1 v to 1v ofb, bfb, fbg ........................................... C 0.3 v to 62 v fbg ............................................................ C1 ma to 2 ma igate ........... m ax (v iid , v csp ) C 10v to max (v iid , v csp ) bgate ....... m ax (v bat , v csn ) C 10v to max (v bat , v csn ) enc , cx , ntc, vm ................................... C 0.3 v to v bias ifb , cl , tmr , iimon , cc ......................... C 0.3 v to v bias bias ............................................. C 0.3 v to min (6 v, v in ) ibmon .................................. C 0.3 v to min (v bias , v csp ) ith ............................................................... C 0.3 v to 6v chrg , flt , rst .......................................... C 0.3 v to 62 v chrg , flt , rst .......................................... C1 ma to 2 ma operating junction temperature range ( note 2) ................................................................. 12 5 c lead temperature ( soldering , 10 sec ) ss op package .................................................. 30 0 c storage temperature range .................. C 65 c to 150 c (note 1) 9 10 top view ufd package 28-lead (4mm 5mm) plastic qfn 11 12 13 28 29 gnd 27 26 25 24 14 23 6 5 4 3 2 1 vm rst iimon ifb enc ibmon cx cl igate ofb csp csn bgate bat bfb fbg gnd in cln cc ith iid tmr gnd f lt chrg bias ntc 7 17 18 19 20 21 22 16 8 15 t jmax = 125c, ja = 43c/w, jc = 4c/w exposed pad (pin 29) is gnd, must be soldered to pcb 1 2 3 4 5 6 7 8 9 10 11 12 13 14 top view gn package 28-lead plastic ssop 28 27 26 25 24 23 22 21 20 19 18 17 16 15 enc ibmon cx cl tmr gnd f lt chrg bias ntc fbg bfb bat bgate ifb iimon rst vm gnd in cln cc ith iid igate ofb csp csn t jmax = 125c, ja = 80c/w, jc = 25c/w p in c on f igura t ion o r d er i n f or m a t ion lead free finish tape and reel part marking* package description temperature range ltc4000eufd-1#pbf ltc4000eufd-1#trpbf 40001 28-lead (4mm 5mm) plastic qfn C40c to 125c ltc4000iufd-1#pbf ltc4000iufd-1#trpbf 40001 28-lead (4mm 5mm) plastic qfn C40c to 125c ltc4000egn-1#pbf ltc4000egn-1#trpbf ltc4000gn-1 28-lead plastic ssop C40c to 125c ltc4000ign-1#pbf ltc4000ign-1#trpbf ltc4000gn-1 28-lead plastic ssop C40c to 125c consult lt c marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. consult lt c marketing for information on non-standard lead based finish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
ltc4000-1 3 40001f e lec t rical c harac t eris t ics the l denotes the specifications which apply over the full operating junction temperature range, otherwise specifications are at t a = 25c. v in = v cln = 3v to 60v unless otherwise noted (notes 2, 3). symbol parameter conditions min typ max units v in input supply operating range l 3 60 v i in input quiescent operating current 0.4 ma i bat battery pin operating current v in 3v, v csn = v csp v bat l 50 100 a battery only quiescent current v in = 0v, v csn = v csp v bat l 10 20 a shutdown enc input voltage low l 0.4 v enc input voltage high l 1.5 v enc pull-up current v enc = 0v C4 C2 C0.5 a enc open circuit voltage v enc = open l 1.5 2.5 v voltage regulation v ifb_reg input feedback voltage l 0.985 1.000 1.010 v ifb input current v ifb = 1.0v 0.1 a v bfb_reg battery feedback voltage l 1.133 1.120 1.136 1.136 1.139 1.147 v v bfb input current v bfb = 1.2v 0.1 a v ofb_reg output feedback voltage l 1.176 1.193 1.204 v ofb input current v ofb = 1.2v 0.1 a r fbg ground return feedback resistance l 100 400 v rechrg(rise) rising recharge battery threshold voltage % of v bfb_reg l 96.9 97.6 98.3 % v rechrg(hys) recharge battery threshold voltage hysteresis % of v bfb_reg 0.5 % v out(inst_on) instant-on battery voltage threshold % of v bfb_reg l 82 86 90 % v lobat falling low battery threshold voltage % of v bfb_reg l 65 68 71 % v lobat(hys) low battery threshold voltage hysteresis % of v bfb_reg 3 % current monitoring and regulation ratio of monitored-current voltage to sense voltage v in,cln 50mv, v iimon /v in,cln v csp,csn 50mv, v ibmon /v csp,csn l 18.5 20 21 v/v v os sense voltage offset v csp,csn 50mv, v csp = 60v or v in,cln 50mv, v in = 60v (note 4) C300 300 v cln, csp, csn common mode range (note 4) l 3 60 v cln pin current 1 a csp pin current v igate = open, v iid = 0v 90 a csn pin current v bgate = open, v bat = 0v 45 a i cl pull-up current for the charge current limit programming pin l C55 C50 C45 a i cl_trkl pull-up current for the charge current limit programming pin in trickle charge mode v bfb < v lobat l C5.5 C5.0 C4.5 a input current monitor resistance to gnd 40 90 140 k charge current monitor resistance to gnd 40 90 140 k a5 error amp offset for the charge current loop (see figure 1) v cl = 0.8v l C10 0 10 mv maximum programmable current limit voltage range l 0.985 1.0 1.015 v
ltc4000-1 4 40001f e lec t rical c harac t eris t ics the l denotes the specifications which apply over the full operating junction temperature range, otherwise specifications are at t a = 25c. v in = v cln = 3v to 60v unless otherwise noted (notes 2, 3). symbol parameter conditions min typ max units charge termination cx pin pull-up current v cx = 0.1v l C5.5 C5.0 C4.5 a v cx,ibmon(os) cx comparator offset voltage, ibmon falling v cx = 0.1v l 0.5 10 25 mv v cx,ibmon(hys) cx comparator hysteresis voltage 5 mv tmr pull-up current v tmr = 0v C5.0 a tmr pull-down current v tmr = 2v 5.0 a tmr pin frequency c tmr = 0.01f 400 500 600 hz tmr threshold for cx termination l 2.1 2.5 v t t charge termination time c tmr = 0.1f l 2.3 2.9 3.5 h t t /t bb ratio of charge terminate time to bad battery indicator time c tmr = 0.1f l 3.95 4 4.05 h/h v ntc(cold) ntc cold threshold v ntc rising, % of v bias l 73 75 77 % v ntc(hot) ntc hot threshold v ntc falling, % of v bias l 33 35 37 % v ntc(hys) ntc thresholds hysteresis % of v bias 5 % v ntc(open) ntc open circuit voltage % of v bias l 45 50 55 % r ntc(open) ntc open circuit input resistance 300 k voltage monitoring and open drain status pins v vm(th) vm input falling threshold l 1.176 1.193 1.204 v v vm(hys) vm input hysteresis 40 mv vm input current v vm = 1.2v 0.1 a i rst,chrg, f lt (lkg) open drain status pins leakage current v pin = 60v 1 a v rst, chrg, f lt ( vol) open drain status pins voltage output low i pin = 1ma l 0.4 v input powerpath control input powerpath forward regulation voltage v iid,csp , 3v v csp 60v l 0.1 8 20 mv input powerpath fast reverse turn-off threshold voltage v iid,csp , 3v v csp 60v, v igate = v csp C 2.5v, ?i igate /? v iid,csp 100a/mv l C90 C50 C20 mv input powerpath fast forward turn-on threshold voltage v iid,csp , 3v v csp 60v, v igate = v iid C 1.5v, ?i igate /? v iid,csp 100a/mv l 40 80 130 mv input gate turn-off current v iid = v csp , v igate = v csp C 1.5v C0.3 a input gate turn-on current v csp = v iid C 20mv, v igate = v iid C 1.5v 0.3 a i igate(fastoff) input gate fast turn-off current v csp = v iid + 0.1v, v igate = v csp C 5v C0.5 ma i igate(faston) input gate fast turn-on current v csp = v iid C 0.2v, v igate = v iid C 1.5v 0.7 ma v igate(on) input gate clamp voltage i igate = 2a, v iid = 12v to 60v, v csp = v iid C 0.5v, measure v iid C v igate l 13 15 v input gate off voltage i igate = C 2a, v iid = 3v to 59.5v, v csp = v iid + 0.5v, measure v csp C v igate l 0.45 0.7 v
ltc4000-1 5 40001f note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the ltc4000-1 is tested under conditions such that t j t a . the ltc4000e-1 is guaranteed to meet specifications from 0c to 85c junction temperature. specifications over the C40c to 125c operating junction temperature range are assured by design, characterization and correlation with statistical process controls. the ltc4000i-1 is guaranteed over the full C40c to 125c operating junction temperature range. note that the maximum ambient temperature consistent with e lec t rical c harac t eris t ics the l denotes the specifications which apply over the full operating junction temperature range, otherwise specifications are at t a = 25c. v in = v cln = 3v to 60v unless otherwise noted (notes 2, 3). symbol parameter conditions min typ max units battery powerpath control battery discharge powerpath forward regulation voltage v bat ,csn , 2.8v v bat 60v l 0.1 8 20 mv battery powerpath fast reverse turn-off threshold voltage v bat ,csn , 2.8v v bat 60v, not charging, v bgate = v csn C 2.5v, ?i bgate /?v bat ,csn 100a/mv l C90 C50 C20 mv battery powerpath fast forward turn-on threshold voltage v bat ,csn , 2.8v v csn 60v, v bgate = v bat C 1.5v, ?i bgate /? v bat ,csn 100a/mv l 40 80 130 mv battery gate turn-off current v bgate = v csn C 1.5v, v csn v bat , v ofb < v out(inst_on) and charging in progress, or v csn = v bat and not charging C0.3 a battery gate turn-on current v bgate = v bat C 1.5v, v csn v bat , v ofb > v out(inst_on) and charging in progress, or v csn = v bat C 20mv 0.3 a i bgate(fastoff) battery gate fast turn-off current v csn = v bat + 0.1v and not charging, v bgate = v csn C 5v C0.5 ma i bgate(faston) battery gate fast turn-on current v csn = v bat C 0.2v, v bgate = v bat C 1.5v 0.7 ma v bgate(on) battery gate clamp voltage i bgate = 2a, v bat = 12v to 60v, v csn = v bat C 0.5v, measure v bat C v bgate l 13 15 v battery gate off voltage i bgate = C 2a, v bat = 2.8v to 59.5v, v csn = v bat + 0.5 v and not charging, measure v csn C v bgate l 0.45 0.7 v bias regulator output and control pins v bias bias output voltage no load l 2.4 2.9 3.5 v ? v bias bias output voltage load regulation i bias = C 0.5ma C0.5 C10 % bias output short-circuit current v bias = 0v C20 ma transconductance of error amp cc = 1v 0.5 ma/v open loop dc voltage gain of error amp cc = open 80 db i ith(pull_up) pull-up current on the ith pin v ith = 0v, cc = 0v C6 C5 C4 a i ith(pull_down) pull-down current on the ith pin v ith = 0.4v, cc = open l 0.5 1 ma open loop dc voltage gain of ith driver ith = open 60 db these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal impedance and other environmental factors. the junction temperature (t j , in c) is calculated from the ambient temperature (t a , in c) and power dissipation (p d , in watts) according to the following formula: t j = t a + (p d ? ja ), where ja (in c/w) is the package thermal impedance. note 3: all currents into pins are positive; all voltages are referenced to gnd unless otherwise noted. note 4: these parameters are guaranteed by design and are not 100% tested.
ltc4000-1 6 40001f typical p er f or m ance c harac t eris t ics battery thresholds: rising recharge, instant-on regulation and falling low battery as a percentage of battery float feedback over temperature cl pull-up current over temperature maximum programmable current limit voltage over temperature input quiescent current and battery quiescent current over temperature battery only quiescent current over temperature input voltage regulation feedback, battery float voltage feedback, output voltage regulation feedback and vm falling threshold over temperature temperature (c) ?60 i bat (a) 100 0.1 0.01 10 1 0.001 100 20 40001 g02 140 40 60 80 ?20 0?40 120 v bat = 3v v bat = 60v v bat = 15v temperature (c) ?60 pin voltage (v) 1.20 1.12 1.18 1.16 1.14 1.00 1.02 1.08 1.06 1.04 1.00 100 20 40001 g03 140 40 60 80 ?20 0?40 120 v bfb_reg v ifb_reg v vm(th) v ofb_reg temperature (c) ?60 v ibmon (v) 1.015 1.010 0.995 1.000 0.990 1.005 0.985 100 20 40001 g06 140 40 60 80 ?20 0?40 120 temperature (c) ?60 percent of v bfb_reg (%) 100 85 95 90 65 75 80 70 60 100 20 40001 g04 140 40 60 80 ?20 0?40 120 v lobat v rechrg(rise) v out(inst_on) temperature (c) ?60 i cl (a) ?45.0 ?47.5 ?52.5 ?50.0 ?55.0 100 20 40001 g05 140 40 60 80 ?20 0?40 120 temperature (c) ?60 ?20?40 i in /i bat (ma) 1.0 0.1 0 80 100 20 40 40001 g01 140 60 0 120 i in i bat v in = v bat = 15v v csn = 15.5v cx comparator offset voltage with v ibmon falling over temperature temperature (c) ?60 v os (v) 300 200 ?100 0 ?200 100 ?300 100 20 40001 g07 140 40 60 80 ?20 0?40 120 v os(csp, csn) v os(in, csn) v max(in,cln) = v max(csp, csn) = 15v current sense offset voltage over common mode voltage range current sense offset voltage over temperature v max(in, cln) /v max(csp, csn) (v) 0 v os (v) 300 200 ?100 0 ?200 100 ?300 40001 g08 60 30 40 50 20103 v os(csp, csn) v os(in, csn) temperature (c) ?60 v cx,ibmon (mv) 20 19 5 6 7 4 9 10 8 18 17 16 15 14 13 12 11 3 100 20 40001 g09 140 40 60 80 ?20 0?40 120
ltc4000-1 7 40001f typical p er f or m ance c harac t eris t ics powerpath forward voltage regulation over temperature charge termination time with 0.1f timer capacitor over temperature ntc thresholds over temperature temperature (c) ?60 t t (h) 3.5 3.3 3.1 2.9 2.7 2.5 2.3 100 20 40001 g10 140 40 60 80 ?20 0?40 120 temperature (c) ?60 percent of v bias (%) 80 65 75 70 45 55 60 50 40 35 30 100 20 40001 g11 140 40 60 80 ?20 0?40 120 v ntc(open) v ntc(hot) v ntc(cold) temperature (c) ?60 v iid,csp / v bat,csn (mv) 14 6 10 12 8 4 2 0 100 20 40001 g12 140 40 60 80 ?20 0?40 120 v iid = v bat = 60v v iid = v bat = 3v v iid = v bat = 15v powerpath turn-off gate voltage over temperature bias voltage at 0.5ma load over temperature i th pull-down current over temperature powerpath fast off, fast on and forward regulation over temperature powerpath turn-on gate clamp voltage over temperature temperature (c) ?60 v iid,csp / v bat,csn (mv) 120 0 60 90 30 ?30 ?60 ?90 100 20 40001 g13 140 40 60 80 ?20 0?40 120 v iid = v bat = 15v temperature (c) ?60 v igate (on) / v bgate(on) (v) 15.0 12.5 13.5 14.5 14.0 13.0 12.0 11.5 11.0 100 20 40001 g14 140 40 60 80 ?20 0?40 120 v iid = v bat = 15v temperature (c) ?60 v csp,igate / v csn,bgate (mv) 600 350 450 550 500 400 300 250 200 100 20 40001 g15 140 40 60 80 ?20 0?40 120 v csp = v csn = 15v temperature (c) ?60 v bias (v) 3.2 2.8 3.0 3.1 2.9 2.7 2.6 2.5 100 20 40001 g16 140 40 60 80 ?20 0?40 120 v in = 60v v in = 15v v in = 3v temperature (c) ?60 i ith(pull-down) (ma) 1.5 0.8 1.0 1.1 1.2 1.3 1.4 0.9 0.7 0.6 0.5 100 20 40001 g17 140 40 60 80 ?20 0?40 120 v ith = 0.4v i th pull-down current vs v ith v ith (v) 0 i ith(pull-down) (ma) 2.5 1.5 2.0 1.0 0.5 0 0.8 0.4 40001 g18 1 0.5 0.6 0.7 0.2 0.3 0.1 0.9
ltc4000-1 8 40001f p in func t ions vm ( pin 1/pin 25): voltage monitor input. high impedance input to an accurate comparator with a 1.193 v threshold (typical). this pin controls the state of the rst output pin. connect a resistor divider (r vm1 , r vm2 ) between the monitored voltage and gnd, with the center tap point con- nected to this pin. the falling threshold of the monitored voltage is calculated as follows: v vm _ rst = r vm1 + r vm2 r vm2 ? 1.193v where r vm2 is the bottom resistor between the vm pin and gnd. tie to the bias pin if voltage monitoring func- tion is not used. rst ( pin 2/ pin 26): high voltage open drain reset output . when the voltage at the vm pin is below 1.193 v, this status pin is pulled low. when driven low, this pin can disable a dc/dc converter when connected to the converters enable pin. this pin can also drive an led to provide a visual status indicator of a monitored voltage. short this pin to gnd when not used. iimon (pin 3/pin 27): input current monitor. the voltage on this pin is 20 times ( typical) the sense voltage (v in,cln ) across the input current sense resistor(r is ), therefore providing a voltage proportional to the input current. connect an appropriate capacitor to this pin to obtain a voltage representation of the time-average input current. leave this pin open when input current monitoring func- tion is not needed. ifb (pin 4/pin 28): input voltage feedback pin. this pin is a high impedance input pin used to sense the input voltage level. in regulation, the input voltage loop sets the voltage on this feedback pin to 1.000 v. when the input feedback voltage drops below 1.000 v, the ith pin is pulled down to reduce the load on the input source. connect this pin to the center node of a resistor divider between the in pin and gnd to set the input voltage regulation level. this regulation level can then be obtained as follows: v in _ reg = r ofb1 r ofb2 + 1 ? ? ? ? ? ? ? 1.000v if the input voltage regulation feature is not used, connect the ifb pin to the bias pin. enc (pin 5/pin 1): enable charging pin. high impedance digital input pin. pull this pin above 1.5 v to enable charg- ing and below 0.5 v to disable charging. leaving this pin open causes the internal 2 a pull-up current to pull the pin to 2.5v (typical). ibmon (pin 6/pin 2): battery charge current monitor. the voltage on this pin is 20 times ( typical) the sense voltage (v csp,csn ) across the battery current sense resistor ( r cs ), therefore providing a voltage proportional to the battery charge current. connect an appropriate capacitor to this pin to obtain a voltage representation of the time-average battery charge current. short this pin to gnd to disable charge current limit feature. cx ( pin 7/pin 3): charge current termination pro- gramming. connect the charge current termination pro- gramming resistor (r cx ) to this pin. this pin is a high impedance input to a comparator and sources 5 a of current. when the voltage on this pin is greater than the charge current monitor voltage (v ibmon ), the chrg pin (qfn/ssop)
ltc4000-1 9 40001f p in func t ions (qfn/ssop) turns high impedance indicating that the cx threshold is reached. when this occurs, the charge current is imme- diately terminated if the tmr pin is shorted to the bias pin, otherwise charging continues until the charge termi- nation timer expires. the charge current termination value is determined using the following formula: i c / x = 0.25a ? r cx ( ) ? 0.5mv r cs where r cs is the sense resistor connected to the csp and the csn pins. note that if r cx = r cl 19.1 k?, where r cl is the charge current programming resistor, then the charge current termination value is one tenth the full charge current, more familiarly known as c/10. short this pin to gnd to disable cx termination. cl ( pin 8/pin 4): charge current limit programming. con - nect the charge current programming resistor (r cl ) to this pin. this pin sources 50 a of current. the regulation loop compares the voltage on this pin with the charge current monitor voltage (v ibmon ), and drives the ith pin accord- ingly to ensure that the programmed charge current limit is not exceeded. the charge current limit is determined using the following formula: i clim = 2.5a ? r cl r cs ? ? ? ? ? ? where r cs is the sense resistor connected to the csp and the csn pins. leave the pin open for the maximum charge current limit of 50mv/r cs . tmr (pin 9/pin 5): charge timer. attach 1 nf of external capacitance ( c tmr ) to gnd for each 104 seconds of charge termination time and 26 seconds of bad battery indicator time. short to gnd to prevent bad battery indicator time and charge termination time from expiring C allowing a continuous trickle charge and top off float voltage regula- tion charge. short to bias to disable bad battery detect and enable c/x charging termination. gnd (pins 10, 28, 29/pins 6, 24): device ground pins. connect the ground pins to a suitable pcb copper ground plane for proper electrical operation. the qfn package exposed pad must be soldered to pcb ground for rated thermal performance. f lt , chrg (pin 11, pin 12/pin 7, pin 8): charge status indicator pins. these pins are high voltage open drain pull down pins. the f lt pin pulls down when there is an under or over temperature condition during charging or when the voltage on the bfb pin stays below the low battery threshold during charging for a period longer than the bad battery indicator time. the chrg pin pulls down during a charging cycle. please refer to the application informa- tion section for details on specific modes indicated by the combination of the states of these two pins. pull up each of these pins with an led in series with a resistor to a voltage source to provide a visual status indicator. short these pins to gnd when not used. bias (pin 13/pin 9): 2.9 v regulator output. connect a capacitor of at least 470nf to bypass this 2.9v regulated voltage output. use this pin to bias the resistor divider to set up the voltage at the ntc pin.
ltc4000-1 10 40001f ntc (pin 14/pin 10): thermistor input. connect a ther- mistor from ntc to gnd, and a corresponding resistor from bias to ntc. the voltage level on this pin determines if the battery temperature is safe for charging. the charge current and charge timer are suspended if the thermistor indicates a temperature that is unsafe for charging. once the temperature returns to the safe region, charging resumes. leave the pin open or connected to a capacitor to disable the temperature qualified charging function. fbg (pin 15/pin 11): feedback ground pin. this is the ground return pin for the resistor dividers connected to the bfb and ofb pins. as soon as the voltage at in is valid (>3 v typical), this pin has a 100 resistance to gnd. when the voltage at in is not valid, this pin is disconnected from gnd to ensure that the resistor dividers connected to the bfb and ofb pins do not continue to drain the battery when the battery is the only available power source. bfb (pin 16/pin 12): battery feedback voltage pin. this pin is a high impedance input pin used to sense the battery voltage level. in regulation, the battery float voltage loop sets the voltage on this pin to 1.136v ( typical). connect this pin to the center node of a resistor divider between the bat pin and the fbg pin to set the battery float voltage. the battery float voltage can then be obtained as follows: v float = r bfb2 + r bfb1 r bfb2 ? 1.136v b at (pin 17/pin 13): battery pack connection. connect the battery to this pin. this pin is the anode of the battery ideal diode driver (the cathode is the csn pin). bgate (pin 18/pin 14): external battery pmos gate drive output. when not charging, the bgate pin drives the external pmos to behave as an ideal diode from the bat pin ( anode) to the csn pin ( cathode). this allows efficient delivery of any required additional power from the battery to the downstream system connected to the csn pin. when charging a heavily discharged battery, the bgate pin is regulated to set the output feedback voltage (ofb pin) to 86% of the battery float voltage (0.974 v typical). this allows the instant-on feature, providing an immediate valid voltage level at the output when the ltc4000-1 is charging a heavily discharged battery. once the voltage on the ofb pin is above the 0.974 v typical value, then the bgate pin is driven low to ensure an efficient charging path from the csn pin to the bat pin. csn ( pin 19/pin 15): charge current sense negative input and battery ideal diode cathode. connect a sense resistor between this pin and the csp pin. the ltc 4000-1 senses the voltage across this sense resistor and regulates it to a voltage equal to 1/20th ( typical) of the voltage set at the cl pin. the maximum regulated sense voltage is 50mv. the csn pin is also the cathode input of the battery ideal diode driver ( the anode input is the bat pin). tie this pin to the csp pin if no charge current limit is desired. refer to the applications information section for complete details. csp (pin 20/pin 16): charge current sense positive input and input ideal diode cathode. connect a sense resis- tor between this pin and the csn pin for charge current sensing and regulation. this input should be tied to csn to disable the charge current regulation function. this pin is also the cathode of the input ideal diode driver (the anode is the iid pin). p in func t ions (qfn/ssop)
ltc4000-1 11 40001f p in func t ions (qfn/ssop) ofb (pin 21/pin 17): output feedback voltage pin. this pin is a high impedance input pin used to sense the output voltage level. in regulation, the output voltage loop sets the voltage on this feedback pin to 1.193 v. connect this pin to the center node of a resistor divider between the csp pin and the fbg pin to set the output voltage when battery charging is terminated and all the output load current is provided from the input. the output voltage can then be obtained as follows: v out = r ofb2 + r ofb1 r ofb2 ? 1.193v when charging a heavily discharged battery ( such that v ofb < v out(inst_on) ), the battery powerpath pmos connected to bgate is regulated to set the voltage on this feedback pin to 0.974v (approximately 86% of the battery float voltage). the instant-on output voltage is then as follows: v out(inst _ on) = r ofb2 + r ofb1 r ofb2 ? 0.974v igate (pin 22/pin 18): input pmos gate drive output. the igate pin drives the external pmos to behave as an ideal diode from the iid pin ( anode) to the csp pin (cathode). iid (pin 23/pin 19): input ideal diode anode. this pin is the anode of the input ideal diode driver ( the cathode is the csp pin). ith (pin 24/pin 20): high impedance control voltage pin. when any of the regulation loops ( input voltage, charge current, battery float voltage or the output voltage) indicate that its limit is reached, the ith pin will sink current ( up to 1ma) to regulate that particular loop at the limit. in many applications, this ith pin is connected to the control/ compensation node of a dc/dc converter. without any external pull-up, the operating voltage range on this pin is gnd to 2.5 v. with an external pull-up, the voltage on this pin can be pulled up to 6 v. note that the impedance connected to this pin affects the overall loop gain. for details, refer to the applications information section. cc (pin 25/pin 21): converter compensation pin. connect an r-c network from this pin to the ith pin to provide a suitable loop compensation for the converter used. refer to the applications information section for discussion and procedure on choosing an appropriate r-c network for a particular dc/dc converter. cln (pin 26/pin 22): input current sense negative input. connect a sense resistor between this pin and the in pin. the ltc4000-1 senses the voltage across this sense resistor and sets the voltage on the iimon pin equal to 20 times this voltage. tie this pin to the in pin if the input current monitoring feature is not used. refer to the applications information section for complete details. in (pin 27/pin 23): input supply voltage: 3 v to 60v. supplies power to the internal circuitry and the bias pin. connect the power source to the downstream system and the battery charger to this pin. this pin is also the positive sense pin for the input current monitor. connect a sense resistor between this pin and the cln pin. tie this pin to cln if the input current monitoring feature is not used. a local 0.1f bypass capacitor to ground is recommended on this pin.
ltc4000-1 12 40001f r c r ntc battery pack r cl c c r cs system load in csn bgate igate cl a2 linear gate driver and voltage clamp enable charging a1 battery ideal diode and instant-on driver input ideal diode driver ith and cc driver ofb ofb a7 a4 cp1 1.193v 1v bfb fbg bat cx ith rst cln cc iid r ofb2 r ofb1 r bfb2 r bfb1 r is dc/dc converter in c iid vm bias tmr f lt chrg c in c cln c l c bat c tmr r vm1 r vm2 c ibmon 40001 bd enc gnd ibmon out csp r cx r3 + ? + ? 1v ? + ? + bias 2a bias 5a/ 50a c iimon iimon ifb in a8 g m = 0.33m a9 g m = 0.33m a11 0.974v g m bfb a6 1.136v a10 1.193v cp5 + ? 1.109v cp6 + ? 0.771v cp2 + ? bias 5a 10mv a5 60k 8mv c bias oscillator logic cp3 + ? + ? cp4 too hot ntc fault too cold ntc ldo, bg, ref ref + ? ? ? + ? + ? g m g m ? + g m g m g m 8mv + ? + ? + ? 60k r ifb2 r ifb1 b lock diagra m figure 1. ltc4000-1 functional block diagram
ltc4000-1 13 40001f o pera t ion overview the ltc4000-1 is designed to simplify the conversion of any externally compensated dc/dc converter into a high performance battery charger with powerpath control. it only requires the dc/dc converter to have a control or external-compensation pin ( usually named vc or ith) whose voltage level varies in a positive monotonic way with its output. the output variable can be either output voltage or output current. for the following discussion, refer to the block diagram in figure 1. the ltc4000-1 includes four different regulation loops: input voltage, charge current, battery float voltage and output voltage ( a4-a7). whichever loop requires the low- est voltage on the ith pin for its regulation controls the external dc/dc converter. the input voltage regulation loop ensures that the input voltage level does not drop below the programmed level. the charge current regulation loop ensures that the pro- grammed battery charge current limit ( using a resistor at cl) is not exceeded. the float voltage regulation loop ensures that the programmed battery stack voltage (us- ing a resistor divider from bat to fbg via bfb) is not exceeded. the output voltage regulation loop ensures that the programmed system output voltage ( using a resistor divider from csp to fbg via ofb) is not exceeded. the ltc4000-1 also provides monitoring pins for the input current and charge current at the iimon and ibmon pins respectively. the ltc4000-1 features an ideal diode controller at the input from the iid pin to the csp pin and a powerpath controller at the output from the bat pin to the csn pin. the output powerpath controller behaves as an ideal diode controller when not charging. when charging, the output powerpath controller has two modes of operation. if v ofb is greater than v out(inst_on) , bgate is driven low. when v ofb is less than v out(inst_on) , a linear regulator implements the instant-on feature. this feature provides regulation of the bgate pin so that a valid voltage level is immediately available at the output when the ltc4000-1 is charging an over- discharged, dead or short faulted battery . the state of the enc pin determines whether charging is enabled. when enc is grounded, charging is disabled and the battery float voltage loop is disabled. charging is enabled when the enc pin is left floating or pulled high (1.5 v) the ltc4000-1 offers several user configurable battery charge termination schemes. the tmr pin can be config- ured for either c/x termination, charge timer termination or no termination. after a particular charge cycle terminates, the ltc4000-1 features an automatic recharge cycle if the battery voltage drops below 97.6% of the programmed float voltage. trickle charge mode drops the charge current to one tenth of the normal charge current ( programmed using a resistor from the cl pin to gnd) when charging into an over discharged or dead battery. when trickle charging, a capacitor on the tmr pin can be used to program a time out period. when this bad battery timer expires and the battery voltage fails to charge above the low battery threshold ( v lobat ), the ltc4000-1 will terminate charging and indicate a bad battery condition through the status pins ( f lt and chrg). the ltc4000-1 also includes an ntc pin, which provides temperature qualified charging when connected to an ntc thermistor thermally coupled to the battery pack. to enable this feature, connect the thermistor between the ntc and the gnd pins, and a corresponding resistor from the bias pin to the ntc pin. the ltc4000-1 also provides a charg- ing status indicator through the f lt and the chrg pins. aside from biasing the thermistor-resistor network, the bias pin can also be used for a convenient pull up voltage. this pin is the output of a low dropout voltage regulator that is capable of providing up to 0.5 ma of current. the regulated voltage on the bias pin is available as soon as the in pin is within its operating range (3v). input ideal diode the input ideal diode feature provides low loss conduction and reverse blocking from the iid pin to the csp pin. this reverse blocking prevents reverse current from the output (csp pin) to the input ( iid pin) which causes unneces- sary drain on the battery and in some cases may result in unexpected dc/dc converter behavior. the ideal diode behavior is achieved by controlling an external pmos connected to the iid pin ( drain) and the
ltc4000-1 14 40001f o pera t ion csp pin ( source). the controller ( a 1) regulates the external pmos by driving the gate of the pmos device such that the voltage drop across iid and csp is 8mv ( typical). when the external pmos ability to deliver a particular current with an 8 mv drop across its source and drain is exceeded, the voltage at the gate clamps at v igate(on) and the pmos behaves like a fixed value resistor (r ds(on) ). input voltage regulation one of the loops driving the ith and cc pins is the input voltage regulation loop (figure 2). this loop prevents the input voltage from dropping below the programmed level. loop to set the battery charge current to 10% of the pro- grammed full-scale value. if the tmr pin is connected to a capacitor or open, the bad battery detection timer is enabled. when this bad battery detection timer expires and the battery voltage is still below v lobat , the battery charger automatically terminates and indicates, via the f lt and chrg pins, that the battery was unresponsive to charge current. once the battery voltage is above v lobat , the charge current regulation loop begins charging in full power constant- current mode. in this case, the programmed full charge current is set with a resistor on the cl pin. depending on available input power and external load conditions, the battery charger may not be able to charge at the full programmed rate. the external load is always prioritized over the battery charge current. the input volt- age programming is always observed, and only additional power is available to charge the battery. when system loads are light, battery charge current is maximized. once the float voltage is achieved, the battery float volt- age regulation loop takes over from the charge current regulation loop and initiates constant voltage charging. in constant voltage charging, charge current slowly declines. charge termination can be configured with the tmr pin in several ways. if the tmr pin is tied to the bias pin, c/x termination is selected. in this case, charging is terminated when constant voltage charging reduces the charge current to the c/x level programmed at the cx pin. connecting a capacitor to the tmr pin selects the charge timer termination and a charge termination timer is started at the beginning of constant voltage charging. charging terminates when the termination timer expires. when continuous charging at the float voltage is desired, tie the tmr pin to gnd to disable termination. upon charge termination, the pmos connected to bgate behaves as an ideal diode from bat to csn. the diode function prevents charge current but provides current to the system load as needed. if the system load can be completely supplied from the input, the battery pmos turns off. while terminated, if the input voltage loop is not in regulation, the output voltage regulation loop takes over to ensure that the output voltage at csp remains in control. figure 2. input voltage regulation loop in cc 1v ith ltc4000-1 in cln r is dc/dc input c cln (optional) ifb c in ? + ? + c c to dc/dc 40001 fo2 r c a4 r ifb2 r ifb1 when the input source is high impedance, the input volt- age drops as the load current increases. in that case there exists a voltage level at which the available power from the input is maximum. for example, solar panels often specify v mp , corresponding to the panel voltage at which maximum power is achieved. with the ltc4000-1 input voltage regulation, this maximum power voltage level can be programmed at the ifb pin. the input voltage regulation loop regulates ith to ensure that the input voltage level does not drop below this programmed level. battery charger overview in addition to the input voltage regulation loop, the ltc4000-1 regulates charge current, battery voltage and output voltage. when a battery charge cycle begins, the battery charger first determines if the battery is over-discharged. if the battery feedback voltage is below v lobat , an automatic trickle charge feature uses the charge current regulation
ltc4000-1 15 40001f o pera t ion the output voltage regulation loop regulates the voltage at the csp pin such that the output feedback voltage at the ofb pin is 1.193v. if the system load requires more power than is available from the input, the battery ideal diode controller provides supplemental power from the battery. when the battery voltage discharges below 97.1% of the float voltage (v bfb < v rechrg(fall) ), the automatic recharge feature initiates a new charge cycle. charge current regulation the first loop involved in a normal charging cycle is the charge current regulation loop (figure 3). this loop drives the ith and cc pins. this loop ensures that the charge current sensed through the charge current sense resistor (r cs ) does not exceed the programmed full charge current . output voltage regulation when charging terminates and the system load is com- pletely supplied from the input, the pmos connected to bgate is turned off. in this scenario, the output voltage regulation loop takes over from the battery float voltage regulation loop (figure 5). the output voltage regulation loop regulates the voltage at the csp pin such that the output feedback voltage at the ofb pin is 1.193v. figure 3. charge current regulation loop figure 4. battery float voltage regulation loop with fbg figure 5. output v oltage regulation loop with fbg csp cc 1v a5 ith ltc4000-1 csp csn r is bat pmos to system ibmon cl c ibmon (optional) c csp + ? ? + + ? ? c c to dc/dc 40001 fo3 r c 60k 50a at normal 5a at trickle bias a9 g m = 0.33m r cl cc 1.136v ith ltc4000-1 bfb bat fbg ? + c c to dc/dc 40001 fo4 r c r bfb2 r bfb1 a6 + ? cc 1.193v ith ltc4000-1 ofb csp fbg ? + c c to dc/dc 40001 fo5 r c r ofb2 r ofb1 a7 + ? battery voltage regulation once the float voltage is reached, the battery voltage regu- lation loop takes over from the charge current regulation loop (figure 4). the float voltage level is programmed using the feedback resistor divider between the bat pin and the fbg pin with the center node connected to the bfb pin. note that the ground return of the resistor divider is connected to the fbg pin. the fbg pin disconnects the resistor divider load when v in < 3 v to ensure that the float voltage resis- tor divider does not consume battery current when the battery is the only available power source. for v in 3v, the typical resistance from the fbg pin to gnd is 100. battery instant-on and ideal diode the ltc4000-1 controls the external pmos connected to the bgate pin with a controller similar to the input ideal diode controller driving the igate pin. when not charg- ing, the pmos behaves as an ideal diode between the bat (anode) and the csn ( cathode) pins. the controller (a2) regulates the external pmos to achieve low loss conduc- tion by driving the gate of the pmos device such that the voltage drop from the bat pin to the csn pin is 8mv. when the ability to deliver a particular current with an 8mv drop across the pmos source and drain is exceeded, the voltage at the gate clamps at v bgate(on) and the pmos behaves like a fixed value resistor (r ds(on) ). the ideal diode behavior allows the battery to provide cur- rent to the load when the input supply is in current limit or the dc/dc converter is slow to react to an immediate load increase at the output. in addition to the ideal diode
ltc4000-1 16 40001f o pera t ion behavior, bgate also allows current to flow from the csn pin to the bat pin during charging. there are two regions of operation when current is flowing from the csn pin to the bat pin. the first is when charging into a battery whose voltage is below the instant-on threshold (v ofb < v out(inst_on) ). in this region of operation, the controller regulates the voltage at the csp pin to be approximately 86% of the final float voltage level (v out(inst_on) ). this feature provides a csp voltage significantly higher than the battery voltage when charging into a heavily discharged battery. this instant-on feature allows the ltc4000-1 to provide sufficient voltage at the output ( csp pin), independent of the battery voltage. the second region of operation is when the battery feedback voltage is greater than or equal to the instant-on threshold (v out(inst_on) ). in this region, the bgate pin is driven low and clamped at v bgate(on) to allow the pmos to turn completely on, reducing any power dissipation due to the charge current. battery temperature qualified charging the battery temperature is measured by placing a nega- tive temperature coefficient ( ntc) thermistor close to the batter y pack. the comparators cp3 and cp4 implement the temperature detection as shown in the block diagram in figure 1. the rising threshold of cp4 is set at 75% of v bias ( cold threshold) and the falling threshold of cp3 is set at 35% of v bias ( hot threshold). when the voltage at the ntc pin is above 75% of v bias or below 35% of v bias then the ltc4000-1 pauses any charge cycle in progress. when the voltage at the ntc pin returns to the range of 40% to 70% of v bias , charging resumes. when charging is paused, the external charging pmos turns off and charge current drops to zero. if the ltc4000-1 is charging in the constant voltage mode and the charge termination timer is enabled, the timer pauses until the thermistor indicates a return to a valid temperature. if the battery charger is in the trickle charge mode and the bad battery detection timer is enabled, the bad battery timer pauses until the thermistor indicates a return to a valid temperature. input uvlo and voltage monitoring the regulated voltage on the bias pin is available as soon as v in 3 v. when v in 3 v, the fbg pin is pulled low to gnd with a typical resistance of 100 and the rest of the chip functionality is enabled. when the in pin is high impedance and a battery is con- nected to the bat pin, the bgate pin is pulled down with a 2a ( typical) current source to hold the battery pmos gate voltage at v bgate(on) below v bat . this allows the battery to power the output. the total quiescent current consumed by ltc4000-1 from the battery when in is not valid is typically 10a. besides the internal input uvlo, the ltc4000-1 also pro- vides voltage monitoring through the vm pin. the rst pin is pulled low when the voltage on the vm pin falls below 1.193v ( typical). on the other hand, when the voltage on the vm pin rises above 1.233 v ( typical), the rst pin is high impedance. one common use of this voltage monitoring feature is to ensure that the converter is turned off when the voltage at the input is below a certain level. in this case, connect the rst pin to the dc/dc converter chip select or enable pin (see figure 6). figure 6. input voltage monitoring with rst connected to the en pin of the dc/dc converter in cp1 ltc4000-1 in cln rst r is vm 40001 fo6 r vm2 r vm1 1.193v + ? in dc/dc converter en
ltc4000-1 17 40001f input ideal diode pmos selection the input external pmos is selected based on the expected maximum current, power dissipation and reverse volt- age drop. the pmos must be able to withstand a gate to source voltage greater than v igate(on) (15 v maximum) or the maximum regulated voltage at the iid pin, whichever is less. a few appropriate external pmos for a number of different requirements are shown at table 1. table 1. pmos part number r ds(on) at v gs = 10v () max id (a) max vds (v) manufacturer sia923edj 0.054 4.5 C20 vishay si9407bdy 0.120 4.7 C60 vishay si4401bdy 0.014 10.5 C40 vishay si4435ddy 0.024 11.4 C30 vishay sud19p06-60 0.060 18.3 C60 vishay si7135dp 0.004 60 C30 vishay note that in general the larger the capacitance seen on the igate pin, the slower the response of the ideal diode driver. the fast turn off and turn on current is limited to C0.5ma and 0.7ma typical respectively ( i igate ( fastoff ) and i igate(faston) ). if the driver can not react fast enough to a sudden increase in load current, most of the extra current is delivered through the body diode of the external pmos. this increases the power dissipation momentarily. it is important to ensure that the pmos is able to withstand this momentary increase in power dissipation. input current monitoring the input current through the sense resistor is available for monitoring through the iimon pin. the voltage on the iimon pin varies with the current through the sense resistor as follows: v iimon = 20 ? i ris ? r is = 20 ? v in C v cln ( ) if the input current is noisy, add a filter capacitor to the cln pin to reduce the ac content. for example, when us- ing a buck dc/dc converter, the use of a c cln capacitor a pplica t ions i n f or m a t ion is strongly recommended. where the highest accuracy is important, pick the value of c cln such that the ac content is less than or equal to 50% of the average voltage across the sense resistor. the voltage on the iimon pin can be filtered further by putting a capacitor on the pin (c iimon ). charge current limit setting and monitoring the regulated full charge current is set according to the following formula: r cs = v cl 20 ? i clim where v cl is the voltage on the cl pin. the cl pin is internally pulled up with an accurate current source of 50a. therefore, an equivalent formula to obtain the charge current limit is: r cl = i clim ? r cs 2.5a ? i clim = r cl r cs ? 2.5a the charge current through the sense resistor is available for monitoring through the ibmon pin. the voltage on the ibmon pin varies with the current through the sense resistor as follows: v ibmon = 20 ? i rcs ? r cs = 20 ? v csp C v csn ( ) the regulation voltage level at the ibmon pin is clamped at 1 v with an accurate internal reference. at 1 v on the ibmon pin, the charge current limit is regulated to the following value: i clim(max) (a) = 0.050v r cs ( ) when this maximum charge current limit is desired, leave the cl pin open or set it to a voltage >1.05 v such that amplifier a 5 can regulate the ibmon pin voltage accurately to the internal reference of 1v. when the output current waveform of the dc/dc converter or the system load current is noisy, it is recommended that
ltc4000-1 18 40001f a capacitor is connected to the csp pin (c csp ). this is to reduce the ac content of the current through the sense resistor (r cs ). where the highest accuracy is important, pick the value of c csp such that the ac content is less than or equal to 50% of the average voltage across the sense resistor. similar to the iimon pin, the voltage on the ibmon pin is filtered further by putting a capacitor on the pin (c ibmon ). this filter capacitor should not be arbitrarily large as it will slow down the overall compensated charge current regulation loop. for details on the loop compensa- tion, refer to the compensation section. battery float voltage programming when the value of r bfb1 is much larger than 100, the final float voltage is determined using the following formula: r bfb1 = v float 1.136v ? 1 ? ? ? ? ? ? r bfb2 when higher accuracy is important, a slightly more ac- curate final float voltage can be determined using the following formula: v float = r bfb1 + r bfb2 r bfb2 ? 1.136v ? ? ? ? ? ? ? r bfb1 r bfb2 ? v fbg ? ? ? ? ? ? where v fbg is the voltage at the fbg pin during float voltage regulation, which accounts for all the current from all resistor dividers that are connected to this pin (r fbg = 100 typical). low battery trickle charge programming and bad battery detection when charging into an over-discharged or dead battery (v bfb < v lobat ), the pull- up current at the cl pin is reduced to 10% of the normal pull-up current. therefore, the trickle charge current is set using the following formula: r cl = i clim(trkl) t r cs 0.25a ? i clim(trkl) = 0.25a t r cl r cs a pplica t ions i n f or m a t ion therefore, when 50a t r cl is less than 1 v, the following relation is true: i clim(trkl) = i clim 10 once the battery voltage rises above the low battery voltage threshold, the charge current level rises from the trickle charge current level to the full charge current level. the ltc4000-1 also features bad battery detection. this detection is disabled if the tmr pin is grounded or tied to bias. however, when a capacitor is connected to the tmr pin, a bad battery detection timer is started as soon as trickle charging starts. if at the end of the bad battery detection time the battery voltage is still lower than the low battery threshold, charging is terminated and the part indicates a bad battery condition by pulling the f lt pin low and leaving the chrg pin high impedance. the bad battery detection time can be programmed ac- cording to the following formula: c tmr (nf) = t badbat (h) t 138.5 note that once a bad battery condition is detected, the condition is latched. in order to re-enable charging, re- move the battery and connect a new battery whose voltage causes bfb to rise above the recharge battery threshold (v rechrg( rise) ). alternatively toggle the enc pin or remove and reapply power to in. c/x detection, charge termination and automatic recharge once the constant voltage charging is reached, there are two ways in which charging can terminate. if the tmr pin is tied to bias, the battery charger terminates as soon as the charge current drops to the level programmed by the cx pin. the c/x current termination level is programmed according to the following formula: r cx = i c / x t r cs 0.25a + 0.5mv ? i c/x = 0.25a t r cx ( ) ? 0.5mv r cs
ltc4000-1 19 40001f a pplica t ions i n f or m a t ion where r cs is the charge current sense resistor connected between the csp and the csn pins. when the voltage at bfb is higher than the recharge threshold (97.6% of float), the c/x comparator is enabled. in order to ensure proper c/x termination coming out of a paused charging condition, connect a capacitor on the cx pin according to the following formula: c cx = 100c bgate where c bgate is the total capacitance connected to the bgate pin. for example, a typical capacitance of 1 nf requires a capaci - tor greater than 100 nf connected to the cx pin to ensure proper c/x termination behavior. if a capacitor is connected to the tmr pin, as soon as the constant voltage charging is achieved, a charge termina- tion timer is started. when the charge termination timer expires, the charge cycle terminates. the total charge termination time can be programmed according to the following formula: c tmr (nf) = t terminate (h) ? 34.6 if the tmr pin is grounded, charging never terminates and the battery voltage is held at the float voltage. note that regardless of which termination behavior is selected, the chrg and f lt pins will both assume a high impedance state as soon as the charge current falls below the pro- grammed c/x level. after the charger terminates, the ltc4000-1 automatically restarts another charge cycle if the battery feedback voltage drops below 97.1% of the programmed final float voltage (v rechrg(fall) ). when charging restarts, the chrg pin pulls low and the f lt pin remains high impedance. output voltage regulation programming the output voltage regulation level is determined using the following formula: r ofb1 = v out 1.193 ? 1 ? ? ? ? ? ? ? r ofb2 as in the battery float voltage calculation, when higher accuracy is important, a slightly more accurate output is determined using the following formula: v out = r ofb1 + r ofb2 r ofb2 ? 1.193v ? ? ? ? ? ? C r ofb1 r ofb2 ? v fbg ? ? ? ? ? ? where v fbg is the voltage at the fbg pin during output voltage regulation, which accounts for all the current from all resistor dividers that are connected to this pin. battery instant-on and ideal diode external pmos consideration the instant-on voltage level is determined using the fol- lowing formula: v out(inst _ on) = r ofb1 + r ofb2 r ofb2 ? 0.974v note that r ofb1 and r ofb2 are the same resistors that program the output voltage regulation level. therefore, the output voltage regulation level is always 122.5% of the instant-on voltage level. during instant-on operation, it is critical to consider the charging pmos power dissipation. when the battery volt- age is below the low battery threshold (v lobat ), the power dissipation in the pmos can be calculated as follows: p trkl = 0.86 ? v float C v bat [ ] ? i clim(trkl) where i clim(trkl) is the trickle charge current limit. on the other hand, when the battery voltage is above the low battery threshold but still below the instant-on thresh- old, the power dissipation can be calculated as follows: p inst _ on = 0.86 ? v float C v bat [ ] ? i clim where i clim is the full scale charge current limit. for example, when charging a 3- cell lithium ion battery with a programmed full charged current of 1 a, the float voltage is 12.6 v, the bad battery voltage level is 8.55 v and the instant-on voltage level is 10.8 v. during instant-on operation and in the trickle charge mode, the worst case
ltc4000-1 20 40001f maximum power dissipation in the pmos is 1.08 w. when the battery voltage is above the bad battery voltage level, then the worst case maximum power dissipation is 2.25w. when overheating of the charging pmos is a concern, it is recommended that the user add a temperature detection circuit that pulls down on the ntc pin. this pauses charg- ing whenever the external pmos temperature is too high. a sample circuit that performs this temperature detection function is shown in figure 7. similar to the input external pmos, the charging external pmos must be able to withstand a gate to source voltage greater than v bgate(on) (15 v maximum) or the maximum regulated voltage at the csp pin, whichever is less. consider the expected maximum current, power dissipation and instant-on voltage drop when selecting this pmos. the pmos suggestions in table 1 are an appropriate starting point depending on the application. float voltage, output voltage and instant-on voltage dependencies the formulas for setting the float voltage, output voltage and instant-on voltage are repeated here: figure 7. charging pmos overtemperature detection circuit protecting pmos from overheating a pplica t ions i n f or m a t ion v float = r bfb1 + r bfb2 r bfb2 ? 1.136v v out = r ofb1 + r ofb2 r ofb2 ? 1.193v v out(inst _ on) = r ofb1 + r ofb2 r ofb2 ? 0.974v in the typical application, v out is set higher than v float to ensure that the battery is charged fully to its intended float voltage. on the other hand, v out should not be programmed too high since v out(inst_on) , the minimum voltage on csp, depends on the same resistors r ofb1 and r ofb2 that set v out . as noted before, this means that the output voltage regulation level is always 122.5% of the instant-on voltage. the higher the programmed value of v out(inst_on) , the larger the operating region when the charger pmos is driven in the linear region where it is less efficient. if r ofb1 and r ofb2 are set to be equal to r bfb1 and r bfb2 respectively, then the output voltage is set at 105% of the float voltage and the instant-on voltage is set at 86% of the float voltage. figure 8 shows the range of possible li-ion battery pack r cs m2 r ntc1 to system rising temperature threshold set at 90c vishay curve 2 ntc resistor thermally coupled with charging pmos voltage hysteresis can be programmed for temperature hysteresis 86mv 10c csn bgate bat csp bias ntc ltc4000-1 162k 20k r3 r4 = r ntc2 at 25c 40001 f07 c bias r ntc2 ltc1540 + ? 2n7002l
ltc4000-1 21 40001f figure 8. possible voltage ranges for v out and v out(inst_on) in ideal scenario nominal output voltage possible output voltage range 75% 86% 40001 f08 possible instant-on voltage range 105% 100% 100% 81.6% nominal float voltage 100% nominal instant-on voltage minimum practical output voltage minimum practical instant-on voltage a pplica t ions i n f or m a t ion output voltages that can be set for v out(inst_on) and v out with respect to v float to ensure the battery can be fully charged in an ideal scenario. taking into account possible mismatches between the resistor dividers as well as mismatches in the various regulation loops, v out should not be programmed to be less than 105% of v float to ensure that the battery can be fully charged. this automatically means that the instant-on voltage level should not be programmed to be less than 86% of v float . battery temperature qualified charging to use the battery temperature qualified charging feature, connect an ntc thermistor, r ntc , between the ntc pin and the gnd pin, and a bias resistor, r3, from the bias pin to the ntc pin (figure 9). thermistor manufacturer datasheets usually include either a temperature lookup table or a formula relating temperature to the resistor value at that corresponding temperature. figure 9. ntc thermistor connection ntc resistor thermally coupled with battery pack r3 r ntc ntc bias bat ltc4000-1 40001 f09 c bias in a simple application, r 3 is a 1% resistor with a value equal to the value of the chosen ntc thermistor at 25c (r 25). in this simple setup, the ltc4000-1 will pause charging when the resistance of the ntc thermistor drops to 0.54 times the value of r 25. for a vishay curve 2 thermistor, this corresponds to approximately 41.5c . as the temperature drops, the resistance of the ntc thermistor rises. the ltc4000-1 is also designed to pause charging when the value of the ntc thermistor increases to three times the value of r 25. for a vishay curve 2 thermistor, this corresponds to approximately C1.5c . with vishay curve 2 thermistor, the hot and cold comparators each have approximately 5 c of hysteresis to prevent oscillation about the trip point. the hot and cold threshold can be adjusted by changing the value of r3. instead of simply setting r3 to be equal to r25, r3 is set according to one of the following formulas: r3 = r ntc at cold_ threshold 3 or r3 = 1.857 ? r ntc at hot _ threshold notice that with only one degree of freedom ( i.e. adjusting the value of r3), the user can only use one of the formulas above to set either the cold or hot threshold but not both. if the value of r3 is set to adjust the cold threshold, the value of the ntc resistor at the hot threshold is then
ltc4000-1 22 40001f a pplica t ions i n f or m a t ion if the user finds that a negative value is needed for r d , the two temperature thresholds selected are too close to each other and a higher sensitivity thermistor is needed. for example, this method can be used to set the hot and cold thresholds independently to 60 c and C5c. using a vishay curve 2 thermistor whose nominal value at 25 c is 100 k, the formula results in r3 = 130 k and r d = 41.2k for the closest 1% resistors values. to increase thermal sensitivity such that the valid charging temperature band is much smaller than 40 c, it is pos- sible to put a ptc ( positive thermal coefficient) resistor in series with r3 between the bias pin and the ntc pin. this ptc resistor also needs to be thermally coupled with the battery. note that this method increases the number of thermal sensing connections to the battery pack from one wire to three wires. the exact value of the nominal ptc resistor required can be calculated using a similar method as described above, keeping in mind that the threshold at the ntc pin is always 75% and 35% of v bias . leaving the ntc pin floating or connecting it to a capacitor disables all ntc functionality. battery v oltage temperature compensation some battery chemistries have charge voltage require- ments that vary with temperature. lead-acid batteries in particular experience a significant change in charge volt- age requirements as temperature changes. for example, manufacturers of large lead-acid batteries recommend a float charge of 2.25 v/ cell at 25c . this battery float voltage, however, has a temperature coefficient which is typically specified at C3.3mv/c per cell. the ltc4000-1 employs a resistor feedback network to program the battery float voltage. manipulation of this network makes for an efficient implementation of vari- ous temperature compensation schemes of battery float voltage. a simple solution for tracking such a linear voltage de- pendence on temperature is to use the lm 234 3- terminal temperature sensor. this creates an easily programmable linear temperature dependent characteristic. equal to 0.179 ? r ntc at cold_threshold. similarly, if the value of r3 is set to adjust the hot threshold, the value of the ntc resistor at the cold threshold is then equal to 5.571 ? r ntc at cold_threshold. note that changing the value of r3 to be larger than r25 will move both the hot and cold threshold lower and vice versa. for example, using a vishay curve 2 thermistor whose nominal value at 25 c is 100 k, the user can set the cold temperature to be at 5 c by setting the value of r3 = 75 k, which automatically then sets the hot threshold at approximately 50c. it is possible to adjust the hot and cold threshold indepen- dently by introducing another resistor as a second degree of freedom (figure 10). the resistor r d in effect reduces the sensitivity of the resistance between the ntc pin and ground. therefore, intuitively this resistor will move the hot threshold to a hotter temperature and the cold threshold to a colder temperature. figure 10. ntc thermistor connection with desensitizing resistor r d ntc resistor thermally coupled with battery pack r3 r ntc ntc bias bat ltc4000-1 r d 40001 f10 c bias the value of r3 and r d can now be set according to the following formula: r3 = r ntc at cold_ threshold C r ntc at hot _ threshold 2.461 r d = 0.219 ? r ntc at cold_ threshold C 1.219 ? r ntc at hot _ threshold note the important caveat that this method can only be used to desensitize the thermal effect on the thermistor and hence push the hot and cold temperature thresholds apart from each other. when using the formulas above,
ltc4000-1 23 40001f a pplica t ions i n f or m a t ion in the circuit shown in figure 12, r bfb1 = Cr set ? (tc ? 4405) and r bfb2 = r bfb1 ? 1.136v v float(25 c) + r bfb1 ? 0.0677 r set ? ? ? ? ? ? ? ? ? ? ? ? C 1.136v where: tc = temperature coefficient in v / c and v float(25 c) is the desired battery float voltage at 25c in v. for example, a 6- cell lead-acid battery has a float charge voltage that is commonly specified at 2.25 v/cell at 25c or 13.5 v, and a C3.3 mv/c per cell temperature coeffi- cient or C19.8 mv/c. substituting these two parameters (tc = C19.8 mv/c and v float(25c) = 13.5 v) and r set = 2.43k into the equation, we obtained the following values: r bfb1 = 210k and r bfb2 = 13.0k. 3-step charging for lead-acid battery the ltc4000-1 naturally lends itself to charging ap- plications requiring a constant current step followed by constant voltage. furthermore, the ltc4000-1 additional features such as trickle charging, bad battery detection and c/x or timer termination makes it an excellent fit for lithium based battery charging applications. figure 13 and table 2 show the normal steps involved in lithium battery charging. figure 13. li-ion typical charging cycle charge time 40001 f13 constant voltage constant current trickle charge charge current battery voltage termination figure 12. battery voltage temperature compensation circuit figure 11. lead-acid 6-cell float charge voltage vs temperature using lm234 with the feedback network temperature (c) ?10 v float (v) 14.4 14.2 13.8 13.4 13.0 14.0 13.6 13.2 12.8 12.6 30 10 50 40001 f11 60 20 0 40 r bfb1 210k r bfb2 13.0k bfb r lm234 v + v ? bat fbg ltc4000-1 r set 2.43k 40001 f12 6-cell lead-acid battery table 2. lithium based battery charging steps step charge method duration trickle charge constant current at a lower current value, usually 1/10th of full charge current until battery voltage rises above low battery threshold time limit set at tmr pin constant current constant current at full charge current until battery voltage reaches float voltage no time limit constant voltage constant voltage terminate either when charge current falls to the programmed level at the cx pin or after the termination timer at tmr pin expires recharge initiate constant current again when battery voltage drops below recharge threshold
ltc4000-1 24 40001f a pplica t ions i n f or m a t ion on the other hand, the ltc4000-1 is also easily configu- rable to handle lead-acid based battery charging. one of the common methods used in lead-acid battery charging is called 3- step charging ( bulk, absorption and float). figure?14 and table 3 summarize the normal steps involved in a typical 3-step charging of a lead-acid battery. figure 14. lead-acid 3-step charging cycle figure 15. 3-step lead-acid circuit configuration charge time 40001 f14 float (storage) bulk charge charge current battery voltage absorption r bfb2 r bfb3 bfb csp cx chrg fbg ltc4000-1 csn bat r cs r cx cl r cl r bfb1 40001 f15 lead-acid battery from dc/dc output when a charging cycle is initiated, the chrg pin is pulled low. the charger first enters the bulk charge step, charg- ing the battery with a constant current programmed at the cl pin: i clim = min 50mv, 2.5a ? r cl ( ) r cs when the battery voltage rises to the absorption voltage level: v absrp = r bfb1 r bfb2 + r bfb3 ( ) r bfb2 r bfb3 + 1 ? ? ? ? ? ? ? 1.136v the charger enters the absorption step, charging the bat- tery at a constant voltage at this absorption voltage level. as the charge current drops to the c/x level: i clim = 0.25a ? r cx ( ) C 0.5mv r cs the chrg pin turns high impedance and now the charger enters the float ( storage) step, charging the battery volt- age at the constant float voltage level: v float = r bfb1 r bfb2 + 1 ? ? ? ? ? ? ? 1.136v table 3. lead-acid battery charging steps step charge method duration bulk charge constant current until battery voltage reaches absorption voltage no time limit absorption constant voltage at the absorption voltage level terminate when charge current falls to the programmed level at the cx pin float (storage) constant voltage at the lower float voltage level (float voltage is lower than the absorption voltage) indefinite recharge initiate bulk charge again when battery voltage drops below recharge threshold figure 15 shows the configuration needed to implement this 3- step lead-acid battery charging with the ltc4000-1.
ltc4000-1 25 40001f a pplica t ions i n f or m a t ion note that in this configuration, the recharge threshold is 97.6% of the float voltage level. when the battery voltage drops below this level, the whole 3- step charging cycle is reinitiated starting with the bulk charge. some systems require trickle charging of an over dis- charged lead-acid battery. this feature can be included using the cl pin of the ltc4000-1. in the configuration shown in figure 15, when the battery voltage is lower than 68% of the absorption level, the pull-up current on the cl pin is reduced to 10% of the normal pull-up cur- rent. therefore, the trickle charge current can be set at the following level: i clim = min 50mv, 0.25a ? r cl ( ) r cs if this feature is not desired, leave the cl pin open to set the regulation voltage across the charge current sense resistor (rcs) always at 50mv. the f lt and chrg indicator pins the f lt and chrg pins in the ltc4000-1 provide status indicators. table 4 summarizes the mapping of the pin states to the part status. table 4. f lt and chrg status indicator f lt chrg status 0 0 ntc over ranged C charging paused 1 0 charging normally 0 1 charging terminated and bad battery detected 1 1 v ibmon < (v c/x C 10mv) where 1 indicates a high impedance state and 0 indicates a low impedance pull-down state. note that v ibmon < (v cx C 10 mv) corresponds to charge termination only if the c/x termination is selected. if the charger timer termination is selected, constant voltage charging may continue for the remaining charger timer period even after the indicator pins indicate that v ibmon < (v cx C 10 mv). this is also true when no termination is selected, constant voltage charging will continue even after the indicator pins indicate that v ibmon < (v cx C 10mv). the bias pin for ease of use the ltc4000-1 provides a low dropout voltage regulator output on the bias pin. designed to provide up to 0.5 ma of current at 2.9 v, this pin requires at least 470 nf of low esr bypass capacitance for stability. use the bias pin as the pull-up source for the ntc resis- tor networks, since the internal reference for the ntc circuitry is based on a ratio of the voltage on the bias pin. furthermore, various 100 k pull-up resistors can be conveniently connected to the bias pin. setting the input v oltage monitoring resistor divider the falling threshold voltage level for this monitoring function can be calculated as follows: r vm1 = v vm _ rst 1.193v C 1 ? ? ? ? ? ? ? r vm2 where r vm1 and r vm2 form a resistor divider connected between the monitored voltage and gnd, with the center tap point connected to the vm pin as shown in figure 6. the rising threshold voltage level can be calculated similarly. input voltage programming connecting a resistor divider from v in to the ifb pin en- ables programming of a minimum input supply voltage. this feature is typically used to program the peak power voltage for a high impedance input source. referring to figure 2, the input voltage regulation level is determined using the following formula: r ifb1 = v in _ reg 1v C 1 ? ? ? ? ? ? r ifb2 where v in_reg is the minimum regulation input voltage level, below which the current draw from the input source is reduced. combining the input voltage programming and the input voltage monitoring resistor divider when connected to the same input voltage node, the input voltage monitoring and the input voltage regulation resistor divider can be combined (see figure 16).
ltc4000-1 26 40001f in this configuration use the following formula to determine the values of the three resistors: r vm3 = 1C 1.193v v vm _ rst ? ? ? ? ? ? v in _ reg 1v ? ? ? ? ? ? r ifb2 r vm4 = 1.193 v in _ reg v vm _ rst ? ? ? ? ? ? C 1 ? ? ? ? ? ? r ifb2 note that for the r vm4 value to be positive, the ratio of v in_reg to v vm_rst has to be greater than 0.838. when the rst pin of the ltc4000-1 is connected to the shdn or run pin of the converter, it is recommended that the value of v in_reg is set higher than the v vm_rst pin by a significant margin. this is to ensure that any voltage noise or ripple on the input supply pin does not cause the rst pin to shut down the converter prematurely, preventing the input regulation loop from functioning as expected. as discussed in the input current monitoring section, noise issues on the input node can be reduced by placing a large filter capacitor on the cln node (c cln ). to further reduce the effect of any noise on the monitoring function, another filter capacitor placed on the vm pin ( c vm ) is recommended. mppt temperature compensation C solar panel example the input regulation loop of the ltc4000-1 allows a user to program a minimum input supply voltage regulation level allowing for high impedance source to provide maximum available power. with typical high impedance sour ce such as a solar panel, this maximum power point varies with temperature. a typical solar panel is comprised of a number of series- connected cells, each cell being a forward-biased p-n junction. as such, the open-circuit voltage ( v oc ) of a solar cell has a temperature coefficient that is similar to a common p-n junction diode, about C2 mv/c. the peak power point voltage (v mp ) for a crystalline solar panel can be approximated as a fixed percentage of v oc , so the temperature coefficient for the peak power point is similar to that of v oc . panel manufacturers typically specify the 25 c values for v oc , v mp and the temperature coefficient for v oc , making determination of the temperature coefficient for v mp of a typical panel straight forward. a pplica t ions i n f or m a t ion in cc 1v ith ltc4000-1 in cln rst r is dc/dc input to dc/dc en pin c cln (optional) c vm ifb vm c in ? + ? + c c to dc/dc compensation pin 40001 f16 r c a4 r ifb2 r vm4 r vm3 cp1 + ? 1.193v figure 16. input voltage monitoring and input voltage regulation resistor divider combined figure 17. temperature characteristic of a solar panel open circuit and peak power point voltages temperature (c) 5 panel voltage v oc(25c) v oc ? v mp v mp(25c) 45 25 40001 f17 55 35 15 v mp v oc v oc temp co. in a manner similar to the battery float voltage temperature compensation, implementation of the mppt temperature compensation can be accomplished by incorporating an lm234 into the input voltage feedback network. using the
ltc4000-1 27 40001f feedback network in figure 18, a similar set of equations can be used to determine the resistor values: r ifb1 = Cr set ? (tc ? 4405) and r ifb2 = r ifb1 ? 1v v mp(25 c) + r ifb1 ? 0.0677 r set ? ? ? ? ? ? ? ? ? ? ? ? C 1v where: tc = temperature coefficient in v /c , and v mp(25c) = maximum power point voltage at 25c in v. typical sinking capability of the ltc4000-1 at the ith pin is 1 ma at 0.4 v with a maximum voltage range of 0 v to 6v. it is imperative that the local feedback of the dc/dc con- verter be set up such that during regulation of any of the ltc4000-1 loops this local loop is out of regulation and sources as much current as possible from its ith/vc pin. for example for a dc/dc converter regulating its output voltage, it is recommended that the converter feedback divider is programmed to be greater than 110% of the output voltage regulation level programmed at the ofb pin . there are four feedback loops to consider when setting up the compensation for the ltc4000-1. as mentioned before these loops are: the input voltage loop, the charge current loop, the float voltage loop and the output volt- age loop. all of these loops have an error amp (a4-a7) followed by another amplifier ( a10) with the intermediate node driving the cc pin and the output of a10 driving the ith pin as shown in figure 19. the most common com- pensation network of a series capacitor (c c ) and resistor (r c ) between the cc pin and the ith pin is shown here. each of the loops has slightly different dynamics due to differences in the feedback signal path. the analytic de- scription of the input voltage regulation loop is included in the appendix section. please refer to the ltc4000 data sheet for the analytic description of the other three loops. in most situations, an alternative empirical approach to compensation, as described here, is more practical. a pplica t ions i n f or m a t ion figure 18. maximum power point voltage temperature compensation feedback network r ifb1 348k r ifb2 8.66k ifb r lm234 v + v ? in v in ltc4000-1 r set 1k 40001 f18 figure 19. error amplifier followed by output amplifier driving cc and ith pins cc ith ltc4000-1 ? + c c 40001 f11 r c a4-a7 g m4-7 = 0.2m a10 g m10 = 0.1m + ? r o4-7 r o10 for example, given a common 36- cell solar panel that has the following specified characteristics: open cir cuit voltage (v oc ) = 21.7v maximum power voltage (v mp ) = 17.6v open- cir cuit voltage temperature coefficient (v oc )?=?C78mv/c as the temperature coefficient for v mp is similar to that of v oc , the specified temperature coefficient for v oc ( tc) of C78mv/ c and the specified peak power voltage ( v mp(25 c) ) of 17.6 v can be inserted into the equations to calculate the appropriate resistor values for the temperature compensa - tion network in figure 18. with r set equal to 1k, then: r set = 1k, r ifb1 = 348k, r ifb2 = 8.66k. compensation in order for the ltc4000-1 to control the external dc/dc converter, it has to be able to overcome the sourcing bias current of the ith or vc pin of the dc/dc converter. the empirical loop compensation based on the analytical expressions and the transfer function from the ith pin to the input and output current of the external dc/dc converter, the user can analytically
ltc4000-1 28 40001f a pplica t ions i n f or m a t ion determine the complete loop transfer function of each of the loops. once these are obtained, it is a matter of analyz- ing the gain and phase bode plots to ensure that there is enough phase and gain margin at unity crossover with the selected values of r c and c c for all operating conditions. even though it is clear that an analytical compensation method is possible, sometimes certain complications render this method difficult to tackle. these complica- tions include the lack of easy availability of the switching converter transfer function from the ith or vc control node to its input or output current, and the variability of parameter values of the components such as the esr of the output capacitor or the r ds(on) of the external pfets. therefore a simpler and more practical way to compensate the ltc4000-1 is provided here. this empirical method involves injecting an ac signal into the loop, observing the loop transient response and adjusting the c c and r c values to quickly iterate towards the final values. much of the detail of this method is derived from application note? 19 which can be found at www.linear.com using an19 in the search box. figure 20 shows the recommended setup to inject an ac-coupled output load variation into the loop. a function generator with 50 output impedance is coupled through a 50/1000 f series rc network to the regulator output. generator frequency is set at 50 hz. lower frequencies may cause a blinking scope display and higher frequen- cies may not allow sufficient settling time for the output transient. amplitude of the generator output is typically set at 5v p-p to generate a 100ma p-p load variation. for lightly loaded outputs ( i out < 100 ma), this level may be too high for small signal response. if the positive and negative transition settling waveforms are significantly different, amplitude should be reduced. actual amplitude is not particularly important because it is the shape of the resulting regulator output waveform which indicates loop stability. a 2- pole oscilloscope filter with f = 10 khz is used to block switching frequencies. regulators without added lc output filters have switching frequency signals at their outputs which may be much higher amplitude than the low frequency settling waveform to be studied. the filter frequency is high enough for most applications to pass the settling waveform with no distortion. oscilloscope and generator connections should be made exactly as shown in figure 20 to prevent ground loop er- rors. the oscilloscope is synced by connecting the chan- nel?b probe to the generator output, with the ground clip of the second probe connected to exactly the same place as channel a ground. the standard 50 bnc sync output of the generator should not be used because of ground loop errors. it may also be necessary to isolate either the generator or oscilloscope from its third wire ( earth figure 20. empirical loop compensation setup i out v in csn csp in cln bat gnd ltc4000-1 50 1w 50 generator f = 50hz r c ith gnd switching converter 40001 f20 bgate ith cc c c 1000f (observe polarity) scope ground clip 10k a 1k 1500pf 0.015f b
ltc4000-1 29 40001f a pplica t ions i n f or m a t ion ground) connection in the power plug to prevent ground loop errors in the scope display. these ground loop errors are checked by connecting channel a probe tip to exactly the same point as the probe ground clip. any reading on channel a indicates a ground loop problem. once the proper setup is made, finding the optimum values for the frequency compensation network is fairly straightforward. initially, c c is made large (1 f) and r c is made small (10 k). this nearly always ensures that the regulator will be stable enough to start iteration. now, if the regulator output waveform is single-pole over damped (see the waveforms in figure 21), the value of c c is re- duced in steps of about 2:1 until the response becomes slightly under damped. next, r c is increased in steps of 2:1 to introduce a loop zero. this will normally improve damping and allow the value of c c to be further reduced. shifting back and forth between r c and c c variations will allow one to quickly find optimum values. if the regulator response is under damped with the initial large value of c c , r c should be increased immediately before larger values of c c are tried. this will normally bring about the over damped starting condition for further iteration. the optimum values for r c and c c normally means the smallest value for c c and the largest value for r c which still guarantee well damped response, and which result in the largest loop bandwidth and hence loop settling that is as rapid as possible. the reason for this approach is that it minimizes the variations in output voltage caused by input ripple voltage and output load transients. a switching regulator which is grossly over damped will never oscillate, but it may have unacceptably large output transients following sudden changes in input voltage or output loading. it may also suffer from excessive overshoot problems on startup or short circuit recovery. to guarantee acceptable loop stability under all conditions, the initial values chosen for r c and c c should be checked under all conditions of input voltage and load current. the simplest way of accomplishing this is to apply load currents of minimum, maximum and several points in between. at each load current, input voltage is varied from minimum to maximum while observing the settling waveform. if large temperature variations are expected for the system, stability checks should also be done at the temperature extremes. there can be significant temperature varia- tions in several key component parameters which affect stability; in particular, input and output capacitor value and their esr, and inductor permeability. the external converter parametric variations also need some consid- eration especially the transfer function from the ith/vc pin voltage to the output variable ( voltage or current). the ltc4000-1 parameters that vary with temperature include the transconductance and the output resistance of the error amplifiers ( a4-a7). for modest temperature varia- tions, conservative over damping under worst-case room temperature conditions is usually sufficient to guarantee adequate stability at all temperatures. one measure of stability margin is to vary the selected values of both r c and c c by 2:1 in all four possible com- binations. if the regulator response remains reasonably well damped under all conditions, the regulator can be considered fairly tolerant of parametric variations. any tendency towards an under damped ( ringing) response indicates that a more conservative compensation may be needed. figure 21. typical output transient response at various stability level generator output regulator output with large c c , small r c with reduced c c , small r c further reduction in c c may be possible improper values will cause oscillations effect of increased r c 40001 f21
ltc4000-1 30 40001f a pplica t ions i n f or m a t ion d esign e xample in this design example, the ltc4000-1 is paired with the lt3845a buck converter to create a 10a, 3- cell lifepo 4 battery charger. the circuit is shown on the front page and is repeated here in figure 22. ? with r ifb2 set at 20k , the input voltage monitoring falling threshold is set at 15 v and the input voltage regulation level is set at 17.6 v according to the following formulas: r vm3 = 1 ? 1.193v 15v ? ? ? ? ? ? 17.6v 1v ? ? ? ? ? ? 20k = 324k r vm4 = 1.193v 17.6v 15v ? ? ? ? ? ? ? 1 ? ? ? ? ? ? 20k = 8.06k ? the input current sense resistor is set at 5 m. there- fore, the voltage at the iimon pin is related to the input current according to the following formula: v iimon = (0.1) ? i ris ? r cl is set at 24.9 k such that the voltage at the cl pin is 1.25v . similar to the iimon pin, the regulation voltage on the ibmon pin is clamped at 1 v with an accurate internal reference. therefore, the charge current limit is set at 10a according to the following formula: i clim(max) = 0.050v r cs = 0.050v 5m = 10a ? the trickle charge current level is consequently set at 1.25a, according to the following formula: i clim(trkl) = 0.25a ? 24.9k 5m = 1.25a ? the battery float voltage is set at 10.8 v according to the following formula: r bfb1 = 10.8 1.136 ? 1 ? ? ? ? ? ? ? 133k 1.13m figure 22. 10.8v at 10a charger for three lifepo 4 cells with solar panel input 1.13m 14.7k 127k 10k 10k 3-cell li-ion battery pack v bat 10.8v float 10a max charge current nths0603 n02n1002j 1.15m 47nf 5m v out 12v, 15a solar panel input <60v open circuit voltage 17.6v peak power voltage 133k csn csp bgate igate bat ofb fbg bfb ntc cx ltc4000-1 ith cc iid 5m lt3845a 100f out v c shdn in rst cln in enc chrg f lt vm 22.1k cl tmr iimon ibmon bias gnd bias bias 24.9k 1f 324k 8.06k ifb 20k 1f 10nf 40001 f22 si7135dp si7135dp 3.0v 1m 0.1f 10nf
ltc4000-1 31 40001f figure 23. charge current regulation loop compensation setup ltc4000-1 10k 1k 40001 f23 0.015f square wave generator f = 60hz ibmon cl 1500pf b a ? the bad battery detection time is set at 43 minutes according to the following formula: c tmr (nf) = t badbat (h) ? 138.5 = 43 60 ? 138.5 = 100nf ? the charge termination time is set at 2.9 hours accord- ing to the following formula: c tmr (nf) = t terminate (h) ? 34.6 = 2.9 ? 34.6 = 100nf ? the c/x current termination level is programmed at 1a according to the following formula: r cx = 1a ? 5m ( ) + 0.5mv 0.25a 22.1k note that in this particular solution, the timer termina- tion is selected since a capacitor connects to the tmr pin. therefore, this c/x current termination level only applies to the chrg indicator pin. ? the output voltage regulation level is set at 12 v accord- ing to the following formula: r ofb1 = 12 1.193 ? 1 ? ? ? ? ? ? ? 127k 1.15m ? the instant - on voltage level is consequently set at 9.79v according to the following formula: v inst _ on = 1150k + 127k 127k ? 0.974v = 9.79v the worst-case power dissipation during instant-on operation can be calculated as follows: ? during trickle charging: p trkl = 0.86 ? v float C v bat [ ] ? i clim _ trkl = 0.86 ? 10.8 [ ] ? 1a = 9.3w ? and beyond trickle charging: p inst _ on = 0.86 ? v float C v bat [ ] ? i clim = 0.86 ? 10.8 C 7.33 [ ] ? 10a = 19.3w therefore, depending on the layout and heat sink avail- able to the charging pmos, the suggested pmos over temperature detection circuit included in figure 7 may need to be included. ? the range of valid temperature for charging is set at C1.5c to 41.5 c by picking a 10 k vishay curve 2 ntc thermistor that is thermally coupled to the battery, and connecting this in series with a regular 10 k resistor to the bias pin. ? for compensation, the procedure described in the empirical loop compensation section is followed. as recommended, first a 1 f c c and 10 k r c is used, which sets all the loops to be stable. for an example of typical transient responses, the charge current regulation loop when v ofb is regulated to v out(inst_on) is used here. figure 23 shows the recommended setup to inject a dc-coupled charge current variation into this particular loop. the input to the cl pin is a square wave at 70hz with the low level set at 120 mv and the high level set at 130 mv, corresponding to a 1.2 a and 1.3 a charge current (100 ma charge current step). therefore, in this particular example the trickle charge current regulation stability is examined. note that the nominal trickle charge current in this example is programmed at 1.25 a (r cl = 24.9k). a pplica t ions i n f or m a t ion
ltc4000-1 32 40001f a pplica t ions i n f or m a t ion with c c = 1 f, r c = 10 k at v in = 20 v, v bat = 7 v, v csp regulated at 9.8 v and a 0.2 a output load condition at csp, the transient response for a 100 ma charge current step observed at ibmon is shown in figure 24. the transient response now indicates an overall under damped system. as noted in the empirical loop compensa- tion section, the value of r c is now increased iteratively until r c = 20 k. the transient response of the same loop with c c = 22nf and r c = 20k is shown in figure 26. figure 24. transient response of charge current regulation loop observed at ibmon when v ofb is regulated to v out(inst_on) with c c = 1f, r c = 10k for a 100ma charge current step 5ms/div ?20 v ibmon (mv) 5mv/div 15 ?10 ?5 0 5 10 ?15 105 15 40001 f24 2520 0 ?10 ?5 ?15 the transient response shows a small overshoot with slow settling indicating a fast minor loop within a well damped overall loop. therefore, the value of c c is reduced iteratively until c c ?=?22 nf. the transient response of the same loop with c c = 22nf and r c = 10k is shown in figure 25. figure 25. transient response of charge current regulation loop observed at ibmon when v ofb is regulated to v out(inst_on) with c c = 22nf, r c = 10k for a 100ma charge current step figure 26. transient response of charge current regulation loop observed at ibmon when v ofb is regulated to v out(inst_on) with c c = 22nf, r c = 20k for a 100ma charge current step 5ms/div ?20 v ibmon (mv) 5mv/div 15 ?10 ?5 0 5 10 ?15 105 15 40001 f25 2520 0 ?10 ?5 ?15 5ms/div ?20 v ibmon (mv) 5mv/div 15 ?10 ?5 0 5 10 ?15 105 15 40001 f26 2520 0 ?10 ?5 ?15 note that the transient response is close to optimum with some overshoot and fast settling. if after iteratively increasing the value of r c , the transient response again indicates an over damped system, the step of reducing c c can be repeated. these steps of reducing c c followed by increasing r c can be repeated continuously until one arrives at a stable loop with the smallest value of c c and the largest value of r c . in this particular example, these values are found to be c c = 22nf and r c = 20k. after arriving at these final values of r c and c c , the stability margin is checked by varying the values of both r c and c c by 2:1 in all four possible combinations. after which the setup condition is varied, including varying the input voltage level and the output load level and the transient response is checked at these different setup conditions. once the desired responses on all different conditions are obtained, the values of r c and c c are noted.
ltc4000-1 33 40001f a pplica t ions i n f or m a t ion this same procedure is then repeated for the other four loops: the input voltage regulation, the output voltage regulation, the battery float voltage regulation and finally the charge current regulation when v ofb > v out(inst_on) . note that the resulting optimum values for each of the loops may differ slightly. the final values of c c and r c are then selected by combining the results and ensuring the most conservative response for all the loops. this usually entails picking the largest value of c c and the smallest value of r c based on the results obtained for all the loops. in this particular example, the value of c c is finally set to 47nf and r c = 14.7k. b oard l a yout c onsidera tions in the majority of applications, the most important param- eter of the system is the battery float voltage. therefore, the user needs to be extra careful when placing and rout- ing the feedback resistor r bfb1 and r bfb2 . in particular, the battery sense line connected to r bfb1 and the ground return line for the ltc4000-1 must be kelvined back to where the battery output and the battery ground are located respectively. figure 27 shows this kelvin sense configuration. for accurate current sensing, the sense lines from r is and r cs (figure 27) must be kelvined back all the way to the sense resistors terminals. the two sense lines of each resistor must also be routed close together and away from noise sources to minimize error. furthermore, cur- rent filtering capacitors should be placed strategically to ensure that very little ac current is flowing through these sense resistors as mentioned in the applications section. the decoupling capacitors c in and c bias must be placed as close to the ltc4000-1 as possible. this allows as short a route as possible from c in to the in and gnd pins, as well as from c bias to the bias and gnd pins. in a typical application, the ltc4000-1 is paired with an external dc/dc converter. the operation of this converter often involves high dv/dt switching voltage as well as high currents. isolate these switching voltages and cur- rents from the ltc4000-1 section of the board as much as possible by using good board layout practices. these include separating noisy power and signal grounds, having a good low impedance ground plane, shielding whenever necessary, and routing sensitive signals as short as pos- sible and away from noisy sections of the board. figure 27. kelvin sense lines configuration for ltc4000-1 40001 f27 v in csn cln in csp bat gnd ltc4000-1 r c ithgnd switching converter bgate ith iidcc c c igate r bfb1 r is r cs r bfb2 bfb fbg system load
ltc4000-1 34 40001f a pplica t ions i n f or m a t ion a ppendix t he l oop t ransfer f unctions when a series resistor (r c ) and capacitor (c c ) is used as the compensation network as shown in figure 19, the transfer function from the input of a4-a7 to the ith pin is simply as follows: v ith v fb (s) = g m4-7 r c ? 1 g m10 ? ? ? ? ? ? c c s + 1 r o4-7 ? c c s ? ? ? ? ? ? ? ? ? ? ? ? where g m4-7 is the transconductance of error amplifier a4- a7, typically 0.5 ma/v; g m10 is the output amplifier (a10) transconductance, r o4-7 is the output impedance of the error amplifier, typically 50 m; and r o10 is the effective output impedance of the output amplifier, typically 10m with the ith pin open circuit. note this simplification is valid when g m10 t r o10 t r o4-7 t c c = a v10 t r o4-7 t c c is much larger than any other poles or zeroes in the system. typically a v10 t r o4-7 t 10 10 with the ith pin open circuit. the exact value of g m10 and r o10 depends on the pull-up current and impedance connected to the ith pin respectively. in most applications, compensation of the loops involves picking the right values of r c and c c . aside from picking the values of r c and c c , the value of g m10 may also be adjusted. the value of g m10 can be adjusted higher by increasing the pull-up current into the ith pin and its value can be approximated as: g m10 = i ith + 5a 50mv the higher the value of g m10 , the smaller the lower limit of the value of r c would be. this lower limit is to prevent the presence of the right half plane zero. even though all the loops share this transfer function from the error amplifier input to the ith pin, each of the loops has a slightly different dynamic due to differences in the feedback signal path. the input voltage regulation loop the feedback signal for the input voltage regulation loop is the voltage on the ifb pin, which is connected to the center node of the resistor divider between the input voltage ( connected to the in pin) and gnd. this voltage is compared to an internal reference (1.000 v typical) by the transconductance error amplifier a4. this amplifier then drives the output transconductance amplifier (a10) to appropriately adjust the voltage on the ith pin driving the external dc/dc converter to regulate the output volt- age observed by the ifb pin. this loop is shown in detail in figure 28. assuming r is << r in << (r ifb1 + r ifb2 ), the simplified loop transmission is as follows: l iv (s) = g m4 r c C 1 g m10 ? ? ? ? ? ? c c s + 1 c c s ? ? ? ? ? ? ? ? ? ? ? ? t gmi p (s) t r in r in c in + c cln ( ) s + 1 ? ? ? ? ? ? t r ifb2 r ifb ? ? ? ? ? ? where gmi p (s) is the transfer function from v ith to the input current of the external dc/dc converter, r in is the equivalent output impedance of the input source, and r ifb ?= r ifb1 + r ifb2 . figure 28. simplified linear model of the input voltage regulation loop in cc 1v ith ltc4000-1 in cln r is dc/dc input c cln (optional) ifb c in ? + ? + c c to dc/dc 40001 f28 r c r ifb2 r ifb1 a4 g m4 = 0.5m a10 g m10 = 0.1m r o4 r o10
ltc4000-1 35 40001f typical a pplica t ions v ? v + lm234 r 6-cell lead-acid battery 210k 14.7k si7135dp 47nf 15m v out 13.5v bsc123no8ns3 bas521 1n4148 b160 0.1f wrth elektronic 74435561100 10h 13.0k csn csp bgate igate bat ofb fbg bfb ntc cx ltc4000-1 ith bias cc iid 442k chrg 2.4k 20m 3m lt3845a sense + burst_en sense ? 33f 3 rst cln in sw bg boost v cc enc v fb v c shdn c ss f set f lt vm ifb iimon ibmon 20k cl tmr gnd bias bias 1f 3.0v 1.10m 100k 348k 10nf 10nf 24.9k 1f 40001 f29 bsc123no8ns3 tg 182k 47f 2.2f 1f 16.2k v in 1.5nf 49.9k sync sgnd 8.66k r lm234 v + v ? solar panel input <40v open circuit voltage 17.6v peak power voltage 1k figure 29. solar panel input, 6-cell lead-acid, 3-step battery charger with 3.3a bulk charge current, 14.1v at 25c absorption voltage and 13.5v at 25c float voltage. temperature compensation of battery float voltage at C19.8mv/c. temperature compensation of solar panel input v mp at C78mv/c with v mp = 17.6v at 25c
ltc4000-1 36 40001f typical a pplica t ions figure 30. 21v at 5a boost converter 5-cell li-ion battery charger for high impedance input sources such as solar cell, fuel cell or wind turbine generator 1.87m 28.7k 107k r ntc 5-cell li-ion battery pack tenergy ssip pack 30104 nths0603 n02n1002j 22nf 10m v out 22v, 5a high impedance input source 8v to 18v with peak power voltage at 11.7v bsc027n04 bas140w si7135dp bsc027n04 107k csn csp bgate igate bat ofb fbg bfb ntc cx ltc4000-1 ith cc iid 1.87m 232k 3.3m ltc3786 v bias v fb 22f 5 150f sw bg tg ithgnd sense + sense ? freq ss rst cln in enc chrg f lt vm 22.1k cl tmr gnd bias 22.1k 1f 100k 7.5k ifb 10k 10k 1f 40001 f30 boost 22f 4 150f intv cc pllinmode run pgood 4.7f 100k 0.1f 0.1f 1nf 100 pa1494.362nl 3.3h 2.5m 100 10f 10k intv cc intv cc si7135dp iimon ibmon 10nf 10nf
ltc4000-1 37 40001f typical a pplica t ions figure 31. 18v to 72v in to 4.2v at 2.0a isolated flyback single-cell li-ion battery charger with 2.9h timer termination and 0.22a trickle charge current 309k 115k r ntc single-cell li-ion battery pack nths0603 n02n1002j v sys 4.4v, 2.5a sia923edj 115k csn csp bgate igate bat ofb bfb fbg ntc ifb cx ltc4000-1 iid cln in vm 309k rst ith enc chrg f lt cc 22.1k cl tmr gnd bias 22.1k 1f 40001 f31 sia923edj 25m 100nf iimon 10nf ibmon 10nf 10k 1f ? ? ? 14.7k 1.5k 13.6k 3.01k bas516 bas516 mmbta42 pdz6.8b 6.8v pds1040 100nf 100k 150k v out v out v cc 0.04 gate fdc2512 isense run ssflt ith ocfbgndsync v cc v in 18v to 72v ltc3805-5 fs 150pf 68 100f 3 0.1f 75k iso1 ps2801-1-k 15.8k 221k 221k 1f 681 v cc 2.2f 2 20m bas516 10nf tr1 pa1277nl
ltc4000-1 38 40001f p ackage descrip t ion please refer to http://www .linear.com/designtools/packaging/ for the most recent package drawings. 4.00 0.10 (2 sides) 2.50 ref 5.00 0.10 (2 sides) note: 1. drawing proposed to be made a jedec package outline mo-220 variation (wxxx-x). 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 top mark (note 6) 0.40 0.10 27 28 1 2 bottom view?exposed pad 3.50 ref 0.75 0.05 r = 0.115 typ r = 0.05 typ pin 1 notch r = 0.20 or 0.35 45 chamfer 0.25 0.05 0.50 bsc 0.200 ref 0.00 ? 0.05 (ufd28) qfn 0506 rev b recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 0.70 0.05 0.25 0.05 0.50 bsc 2.50 ref 3.50 ref 4.10 0.05 5.50 0.05 2.65 0.05 3.10 0.05 4.50 0.05 package outline 2.65 0.10 3.65 0.10 3.65 0.05 ufd package 28-lead plastic qfn (4mm 5mm) (reference ltc dwg # 05-08-1712 rev b)
ltc4000-1 39 40001f information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. p ackage descrip t ion please refer to http://www .linear.com/designtools/packaging/ for the most recent package drawings. .386 ? .393* (9.804 ? 9.982) gn28 rev b 0212 1 2 3 4 5 6 7 8 9 10 11 12 .229 ? .244 (5.817 ? 6.198) .150 ? .157** (3.810 ? 3.988) 202122232425262728 19 18 17 13 14 16 15 .016 ? .050 (0.406 ? 1.270) .015 .004 (0.38 0.10) 45 0 ? 8 typ .0075 ? .0098 (0.19 ? 0.25) .0532 ? .0688 (1.35 ? 1.75) .008 ? .012 (0.203 ? 0.305) typ .004 ? .0098 (0.102 ? 0.249) .0250 (0.635) bsc .033 (0.838) ref .254 min recommended solder pad layout .150 ? .165 .0250 bsc .0165 .0015 .045 .005 * dimension does not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side ** dimension does not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side inches (millimeters) note: 1. controlling dimension: inches 2. dimensions are in 3. drawing not to scale 4. pin 1 can be bevel edge or a dimple gn package 28-lead plastic ssop (narrow .150 inch) (reference ltc dwg # 05-08-1641 rev b)
ltc4000-1 40 40001f linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com linear technology corporation 2012 lt 0712 ? printed in usa r ela t e d p ar t s typical a pplica t ion part number description comments ltc4000 high voltage high current controller for battery charging and power management similar to ltc4000-1 with input current regulation ltc3789 high efficiency, synchronous, 4 switch buck-boost controller improved ltc3780 with more features lt3845 high voltage synchronous current mode step-down controller with adjustable operating frequency for medium/high power, high efficiency supplies LT3650 high voltage 2a monolithic li-ion battery charger 3mm w 3mm dfn-12 and msop-12 packages lt3651 high voltage 4a monolithic li-ion battery charger 4a synchronous version of LT3650 family lt3652/ lt3652hv power tracking 2a battery chargers multi-chemistry, onboard termination ltc4009 high efficiency, multi-chemistry battery charger low cost version of ltc4008, 4mm w 4mm qfn-20 ltc4012 high efficiency, multi-chemistry battery charger with powerpath control similar to ltc4009 adding powerpath control lt3741 high power, constant current, constant voltage, step-down controller thermally enhanced 4mm w 4mm qfn and 20-pin tssop figure 32. solar panel input 6v to 36v in to 14.4v at 4.5a buck boost converter 4-cell lifepo 4 battery charger with 2.9h timer termination and 0.22a trickle charge current 1.37m 14.7k 26.7k 10k r ntc 4-cell lifepo 4 battery pack nths0603 n02n1002j q2: sir422dp q3: sir496dp q4: sir422dp q5: sir496dp 100nf 10m 309k v out 15v, 5a si7135dp 118k csn csp bgate igate bat ofb fbg bfb ntc ltc4000-1 ith cc iid 154k bzt52c5v6 4m 0.01 ltc3789 extv cc v fb 0.22f intv cc intv cc boost2 boost1 tg2sw2 mode/pllin pgood ithrun ss sgnd pgnd1 freq rst cln in enc chrg f lt vm 1f 210k 16.2k ifb 8.66k v outsns i osense ? i osense + sense ? sense + 8.06k 100k 10f 10f dfls160 b240a dfls160 40001 f32 270f 3.3f 5 330f 2 22f 2 v in v insns 1f ilim 121k si7343dp bg2 bg1sw1tg1 q5 q3 q2 q4 b240a 0.01f 0.22f 1.24k 0.01 1.24k 5.6 390pf ihlp6767gz er4r7m01 4.7h 3.6 1800pf r lm234 v + v ? solar panel input <40v open circuit voltage 11.8v peak power voltage 1k cx 22.1k cl tmr iimon ibmon gnd bias 18.2k 1f 10nf 0.1f 10nf

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